AI02024B

1.3V

OUT

CL = 30pF or 60pF or 100pF

CL includes JIG capacitance

3.3k

Ω

1N914

DEVICE

UNDER

TEST

Figure 4. AC Testing Load Circuit

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

6

pF

Output Capacitance

12

pF

2. This parameter is sampled only and not tested 100%.

°C, f = 1 MHz )

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitiveand inductiveloading of the device at the

output. The associated transient voltage peaks can

be suppressed by complying with the two line

output control and by properly selected decoupling

capacitors. It is recommended that a 1

µF ceramic

of low inherent inductance and should be placed

as close to the device as possible. In addition, a

4.7

µF bulk electrolytic capacitor should be used

bulk capacitor should be located near the power

supplyconnection point.The purpose of the bulk

capacitor is to overcome the voltage drop caused

by the inductive effects of PCB traces.

AI01822

3V

High Speed

0V

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 3. AC Testing Input Output Waveform

High Speed

Standard

Input Rise and Fall Times

≤ 10ns

≤ 20ns (10% to 90%)

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

Input and Output Timing Ref. Voltages

1.5V

0.8V and 2V

Table 5. AC Measurement Conditions

4/12

M27C516