VDIP1 Vinculum VNC1L Prototyping Module

Datasheet Version 0.92

© Future Technology Devices Intl Ltd. 2006-2007

Page 

2.5ParallelFIFOInterfaceSignalDescriptionsandTimingDiagrams

Ta�le � - Data and Control ��us �ignal Mode �ptions - Parallel FIF� Inter�ace

Pin No.

Name

Type

Description

6

D0

I/�

FIF� Data ��us ��it 0

8

D1

I/�

FIF� Data ��us ��it 1

9

D2

I/�

FIF� Data ��us ��it 2

10

D�

I/�

FIF� Data ��us ��it �

11

D4

I/�

FIF� Data ��us ��it 4

12

D�

I/�

FIF� Data ��us ��it �

1�

D6

I/�

FIF� Data ��us ��it 6

14

D7

I/�

FIF� Data ��us ��it 7

1�

RXF#

��TP�T

When high�� do not read data �rom the FIF�. When low�� there is data availa�le in the FIF� which can

b������by�����b��gR�#l�����h��h�gh�g����

16

TX�#

��TP�T

When high�� do not write data into the FIF�. When low�� data can �e written into the FIF� �y stro�ing

W� high�� then low.

17

R�#

INP�T

���bl���h��u�������FIFO����by�����0����7�h��l���F���h���h���x�FIFO����by��(���v��l-

�bl�)����m�h�������v�FIFObu������h��R�#g�������mh�gh��l���

19

W�

INP�T

Writes the data �yte on the D0...D7 pins into the transmit FIF� �u��er when W� goes �rom high to low.

Figure � - FIF� �ead Cycle

RXF#

RD#

D[7...0]

T3

T1

T5

T6

T2

T4

Valid Data

Ta�le 6 - FIF� �ead Cycle Timings

Time

Description

Min

Max

Unit

T1

�D �ctive Pulse Width

�0

-

ns

T2

�D to �D Pre-Charge Time

�0 + T6

-

ns

T�

�D �ctive to Valid Data*

20

�0

ns

T4

Valid Data Hold Time �rom �D Inactive* 0

-

ns

T�

R�I�����v���RXF#

0

2�

ns

T6

�XF Inactive ��ter �D Cycle

80

-

ns

* Load = �0pF