VDIP1 Vinculum VNC1L Prototyping Module

Datasheet Version 0.92

© Future Technology Devices Intl Ltd. 2006-2007

Page 10

register (�1�) is written to. During the �PI write cycle a �yte o� data can �e input to �PI Data In on the ne�t cloc� cycle

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chec�ed to see i� the data read was accepted. � �0� level on �PI Data �ut means that the data write was accepted. �

�1� indicates that the internal �u��er is �ull�� and the write should �e repeated. �emem�er that C� must �e held low �or at

least one cloc� period �e�ore �eing ta�en high again to continue with the ne�t read or write cycle.

Figure 7 - �PI �lave Data Timing Diagrams

T1

T2

T�

T4

T�

T6

T7

�PICLK

�PIC� /

�PI D�T� IN

�PI D�T� ��T

Ta�le 9 - �PI �lave Data Timing

Time

Description

Min

Typical Max

Unit

T1

�PICLK Period

8�

-

-

ns

T2

�PICLK High

20

-

-

ns

T�

�PICLK Low

20

-

-

ns

T4

Input �etup Time

10

-

-

ns

T�

Input Hold Time

10

-

-

ns

T6

�utput Hold Time

2

-

-

ns

T7

�utput Valid Time

-

-

20

ns

Ta�le 10 - �tatus �egister (�DD = �1�)

Bit

Description

0

RXF#

1

TX�#

2

-

�

-

4

RXFIRQ��

�

TX�IRQ��

6

-

7

-