USB2513 datasheet(18/48 Pages) SMSC

18 / 48 page

USB 2.0 High-Speed 3-Port Hub Controller

Datasheet

Revision 1.98 (11-19-07)

SMSC USB2513

DATASHEET

Chapter 4 Configuration Options

4.1

3-Port Hub

SMSC’s USB 2.0 3-Port Hub is fully specification compliant to the Universal Serial Bus Specification

Revision 2.0 April 27, 2000 (12/7/2000 and 5/28/2002 Errata). Please reference Chapter 10 (Hub

Specification) for general details regarding Hub operation and functionality.

For performance reasons, the 3-Port Hub provides 1 Transaction Translator (TT) per port (defined as

Multi-TT configuration), divided into 4 non-periodic buffers per TT.

4.1.1

Hub Configuration Options

The SMSC Hub supports a large number of features (some are mutually exclusive), and must be

configured in order to correctly function when attached to a USB host controller. There are three

principal ways to configure the hub: SMBus, EEPROM, or by internal default settings (with or without

pin strapping option over-rides). In all cases, the configuration method will be determined by the

CFG_SEL2, CFG_SEL1 and CFG_SEL0 pins immediately after RESET_N negation.

4.1.1.1

Power Switching Polarity

The selection of active state “polarity” for the PRTPWR pins is made by a strapping option only (the

PRTPWR_POL pin).

Note: If PRTPWR_POL is not an available pin on the package, the hub will support active high power

controllers only!

4.1.2

VBus Detect

According to Section 7.2.1 of the USB 2.0 Specification, a downstream port can never provide power

to its D+ or D- pull-up resistors unless the upstream port’s VBUS is in the asserted (powered) state.

The VBUS_DET pin on the Hub monitors the state of the upstream VBUS signal and will not pull-up

the D+ resistor if VBUS is not active. If VBUS goes from an active to an inactive state (Not Powered),

Hub will remove power from the D+ pull-up resistor within 10 seconds.

4.2

36 QFN and 48 QFN Feature Differences

Table 4.1 36 QFN and 48 QFN Feature Differences

36 QFN

48 QFN

FEATURE

N/A

Available

48MHz clock input mode

N/A

Available

External 1.8V regulators

N/A

Available

Port LED Indicators

N/A

Available

Port Swap Strapping Options

Available

N/A

Only Active High Port Power Control is supported in 36 QFN package

Available

N/A

Boost Default Level is used; see Table 4.2, "Internal Default, EEPROM and

SMBus Register Memory Map"

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