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USB2513 数据表(PDF) 35 Page - SMSC Corporation

部件名 USB2513
功能描述  USB 2.0 High-Speed 3-Port Hub Controller
PDF  48 Pages
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制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

USB2513 数据表(HTML) 35 Page - SMSC Corporation

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USB 2.0 High-Speed 3-Port Hub Controller
Datasheet
SMSC USB2513
35
Revision 1.98 (11-19-07)
DATASHEET
Block Read
A Block Read differs from a block write in that the repeated start condition exists to satisfy the I2C
specification’s requirement for a change in the transfer direction.
Figure 4.2 Block Read
4.4.2
Invalid Protocol Response Behavior
Registers that are accessed with an invalid protocol are not updated. A register is only updated
following a valid protocol. The only valid protocols are Write Block and Read Block, which are
described above.
The Hub only responds to the hardware selected Slave Address.
Attempting to communicate with the Hub over SMBus with an invalid slave address or invalid protocol
results in no response, and the SMBus Slave Interface returns to the idle state.
The only valid registers that are accessible by the SMBus slave address are the registers defined in
the Registers Section. See Section 4.4.3 for the response to undefined registers.
4.4.3
General Call Address Response
The Hub does not respond to a general call address of 0000_000b.
4.4.4
Slave Device Time-Out
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress
and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that
have detected this condition must reset their communication and be able to receive a new START
condition no later than 35ms (TTIMEOUT, MAX).
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically
resets its communications port after a start or stop condition. The Slave Device Time-Out must
be implemented.
4.4.5
Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch
the SCLK.
4.4.6
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing
in the “Timing Diagram” section.
Block Read
1
S
S
Slave Address
Register Address
Wr
A
17
1
1
8
A
1
Slave Address
Rd
A
71
1
81
1
1
88
P
1
81
A
A
A
A
Byte Count = N
Data byte 1
Data byte 2
Data byte N
...



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