ST7LITEU09 datasheet(37/115 Pages) STMICROELECTRONICS

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

8.4.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS

Read/Write

Reset Value: 0000 0x00 (0xh)

Bit 7 = Reserved, must be kept cleared.

Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-

justment bits

These bits, as well as CR[9:2] bits in the RCCR

adjust the RC oscillator frequency and to obtain

the required accuracy. Refer to section 7.1 on

page 22.

Bits 4:3 = Reserved, must be kept cleared.

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared when read. See WDGRF flag de-

scription in Section 11.1 for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Note: If the selected clock source is one of the two

internal ones, and if VDD remains below the select-

ed LVD threshold during less than TAWU_RC (33µs

typ.), the LVDRF flag cannot be set even if the de-

vice is reset by the LVD. If the selected clock

source is the external clock (CLKIN), the flag is

never set if the reset occurs during Halt mode. In

run mode the flag is set only if fCLKIN is greater

than 10MHz.

Bit 1 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit is set. Refer to Figure

21 for additional details

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 0 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag is

set. The pending interrupt information is automati-

cally cleared when software enters the AVD inter-

rupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

AVD THRESHOLD SELECTION REGISTER

(AVDTHCR)

Read/Write

Reset Value: 0000 0011 (03h)

Bits 7:5 = CK[2:0] internal RC Prescaler Selection

Refer to Section 7.1 INTERNAL RC OSCILLATOR

ADJUSTMENT on page 22.

Bits 4:2 = Reserved, must be kept cleared.

Bits 1:0 = AVD[1:0] AVD Threshold Selection

These bits are set and cleared by software and set

by hardware after a reset. They select the AVD

threshold.

Table 12. AVD Threshold Selection bits

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

CR1 CR0

LVDRF AVDF AVDIE

CK2 CK1 CK0

AVD1 AVD0

Functionality

Low

Medium

High

AVD off

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