SAP51D-B-G1-R datasheet(12/67 Pages) RENESAS

12 / 67 page

SAP51 / SAP5S Datasheet

January 28, 2016

Following device functions are handled by the different blocks of the SAP5:

RECEIVER

The RECEIVE block converts the analog telegram waveform from the AS-i bus to a digital pulse-

coded signal that can be processed further by a digital UART circuit.

The RECEIVE block is directly connected to the AS-i line pins LTGP and LTGN. It converts the

differential AS-i telegram to a single-ended signal and removes the DC offset by high-pass filtering.

To adapt quickly to changing signal amplitudes in telegrams from different network users, the

amplitude of the first telegram pulse is measured by a 3-bit flash ADC and the threshold of a positive

and a negative comparator is set accordingly to about 50% of the measured level. The comparators

generate the p_pulse and n_pulse signals.

TRANSMITTER

The transmit block transforms a digital response signal to a correctly shaped send current signal,

which is applied to the AS-i bus. Due to the inductive network behavior of the network, the changing

send current induces voltage pulses on the network line that overlay the DC operating voltage. The

voltage pulses must have sin²-wave shapes; therefore the send current shape must follow the

integral of the sin²-wave function.

UART /

MAIN STATE

MACHINE /

EEPROM

EEPROM write access and other I/O operations of the Main State Machine are supported in Slave

Mode only (see the description of the general SAP5 operational modes below). In Master Mode, the

SAP5 is basically equivalent to a physical layer transceiver.

If Slave Mode is activated, the UART demodulates the received telegrams, verifies telegram syntax

and timing, and controls a register interface to the Main State Machine. After reception of a correct

telegram, the UART generates appropriate Receive Strobe signals, which tell the Main State

Machine to start further processing. The Main State Machine decodes the telegram information and

starts respective I/O processes or EEPROM access. A second register interface is used to send data

back to the UART for construction of a telegram response. The UART modulates the response data

into a Manchester-II-coded bit stream that is used to control the TRANSMITTER unit.

ELECTRONIC

INDUCTOR

The electronic inductor is basically a gyrator circuit. It provides an inductive behavior between the

SAP5 pins LTGP and UOUT while the inductance is controlled by the capacitor on the CDC pin. The

inductor decouples the power regulator of the SAP5 as well as the external load circuit from the AS-i

bus and hence prevents crosstalk or switching noise from disturbing the telegram communication on

the bus.

The AS-Interface Complete Specification describes the input impedance behavior of a slave module

via an equivalent circuit that consists of R, L, and C in parallel. For example, a slave module in

Extended Address Mode must have R > 13.5k

Ω, L > 13.5mH, and C < 50pF. The electronic inductor

of the SAP5 delivers values that are well within the required ranges for output currents up to 55mA

(VLTGP>24V). More detailed parameters can be found in section 5.1.

The electronic inductor requires an external capacitor of 10µF at the UOUT pin for stability.

POWER

SUPPLY

The power supply block consists of a band-gap referenced 5V-regulator as well as other reverence

voltage and bias current generators for internal use. The 5V regulator requires an external capacitor

at pin U5R of at least 100nF for stability. It can source up to 4mA for external use, however the

power dissipation and the resulting device heating become a major concern if too much current is

drawn from the regulator. See section 5.1.

SAP51D-B-G1-R 数据表(PDF) 12 Page - Renesas Technology Corp

SAP51D-B-G1-R 数据表(HTML) 12 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载