1

PS8889D

10/03/07

Features

• Supports data rates up to 3.2Gbps on each lane

• Adjustable Transmiter De-Emphasis & Amplitude

• Adjustable Receiver Equalization

• Spectrum Reference Clock Buffer Output

• Optimized for SATAi/m applications

• Input signal level detection & output squelch on all channels

• 100-Ohm Differential CML I/O’s

• Low Power (100mW per Channel)

• Standby Mode – Power Down State

• Packaging (Pb-free & Green):48-contact TQFN

Description

Pericom Semiconductor’s PI2EQX3232B is a low power, signal

Re-Driver. The device provides programmable equalization,

amplification, and de-emphasis, to optimize performance over a

variety of physical mediums by reducing Inter-Symbol Interference

(ISI). PI2EQX3232B supports four 100-Ohm Differential CML

data I/O’s between the Protocol ASIC to a switch fabric, across

a backplane, or to extend the signals across other distant data

pathways on the user’s platform.

The integrated equalization circuitry provides flexibility with

signal integrity of the signal before the Re-Driver. Whereas the

integrated de-emphasis circuitry provides flexibility with signal

integrity of the signal after the Re-Driver.

A low-level input signal detection and output squelch function

is provided for all four channels. Each channel operates fully

independantly. When a channel is enabled (EN_x=1) and

operating, that channels input signal level (on xI+/-) determines

whether the output is enabled. If the input level of the channel

falls below the active threshold level (Vth-) then the output driver

switches off, and the pin is pulled to VDD via a high impedance

resistor. If the input level of the channel falls below the active

threshold level (Vth-) then the outputs are driven to the common

mode voltage.

In addition to providing signal re-conditioning, Pericom’s

PI2EQX3232B also provides power management Stand-by mode

operated by an Enable pin.

Block Diagram

PI2EQX3232B

3.2Gbps, 2-Port, SATAi/m, Serial Re-Driver

Pin Description

EN_x

Power

Management

xI+

CML

xI-

xO+

xO-

CML

Limiting

Amp

Equalizer

SEL_EQ

CKIN-

CKIN+

OUT-

OUT+

SEL_OL_x

SEL_DE_ x

-- Repeated 4 times --

Buffer

EN_

CLK

IREF

Signal Detect

_x

1

2

3

4

5

6

7

8

9

10

11

12

VDD

AI+

AI-

VDD

BO+

BO-

VDD

CI+

CI-

DO+

DO-

GND

AO

VDD

BI+

VDD

CO+

CO-

VDD

DI+

DI-

36

35

34

33

32

31

30

29

28

27

26

25

GND

VDD

AO+

BI-

-

07-0225