2

PS8889D

10/03/07

PI2EQX3232B

3.2Gbps, 2-Port, SATAi/m,

Serial Re-Driver

Pin Description

Pin #

Pin Name

I/O

Description

1

AI+

I

Positive CML Input Channel A with internal 50Ω pull down

2

AI-

I

Negative CML Input Channel A with internal 50Ω pull down

36

AO+

O

Positive CML Output Channel A internal 50Ω pull up to VDD during normal opera-

tion and 2kΩ when EN_A=0. Drives to output common mode voltage when input is

35

AO-

O

Negative CML Output Channel A with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_A=0. Drives to output common mode voltage when

33

BI+

I

Positive CML Input Channel B with internal 50Ω pull down

32

BI-

I

Negative CML Input Channel B with internal 50Ω pull down

4

BO+

O

Positive CML Output Channel B with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_B=0. Drives to output common mode voltage when

5

BO-

O

Negative CML Output Channel B with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_B=0. Drives to output common mode voltage when

7

CI+

I

Positive CML Input Channel C with internal 50Ω pull down

8

CI-

I

Negative CML Input Channel C with internal 50Ω pull down

14

15

CKIN+

CKIN-

I

I

Differential Input Reference Clock

30

CO+

O

Positive CML Output Channel C with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_C=0. Drives to output common mode voltage when

29

CO-

O

Negative CML Output Channel C with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_C=0. Drives to output common mode voltage when

27

DI+

I

Positive CML Input Channel D with internal 50Ω pull down

26

DI-

I

Negative CML Input Channel D with internal 50Ω pull down

10

DO+

O

Positive CML Output Channel D with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_D=0. Drives to output common mode voltage when

11

DO-

O

Negative CML Output Channel C with internal 50Ω pull up to VDD during normal

operation and 2kΩ when EN_D=0. Drives to output common mode voltage when

41, 40, 39, 38

EN_

[A,B,C,D]

I

Active HIGH LVCMOS signal input pins, when HIGH, it enables the CML output.

When LOW, it disables the CML output (x0+, x0-) to HI-z state. Both x0+ & x0- out-

13

EN_CLK

I

Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTx-

outputs. When LOW, it disables these outputs, with 50Ω to ground termination.

25, Center Pad

GND

PWR

Supply Ground

24

IREF

O

External 475Ω resistor connection to set the differential output current

22

23

OUT0+

OUT1-

O

O

Differential Reference Clock Output

47

SEL_EQ_A

I

Selection pins for equalizer (see Amplifier Configuration Table)

w/ 50kΩ internal pull up

46

SEL_EQ_B

I

16

SEL_EQ_C

I

17

SEL_EQ_D

I

07-0225