NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

Tamb = -40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V

unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

VRX to VSX, VRY to VSY; on

falling input between VRX = input

switching threshold, and VSX

output falling to 50 % VCC

-

100

-

ns

VRX to VSX, VRY to VSY; on

rising input between VRX = input

switching threshold, and VSX

output reaching 50 % VCC

-

95

-

ns

Input capacitance

Ci

input capacitance

effective input capacitance of

any signal pin measured by

incremental bus rise times;

guaranteed by design, not

production tested

-

-

10

pF

Table 6. Characteristics...continued

[1]

This bus pull-up current specification is intended to assist design of the bus pull-up resistor. It is not a specification of the sink capability (see VOL under

sub-section "Output logic LOW level"). The maximum static sink current for a Standard/Fast-mode I2C-bus is 3 mA and PCA9600 is guaranteed to sink

3 mA at SX/SY when its pins are holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9600 may source a

current between 0 mA and 1 mA maximum. When that other external device is driving LOW it will pull the bus connected to SX or SY down to, or below,

the 0.4 V level referenced in the I2C-bus specification and in these test conditions. Then that device must be able to sink up to 1 mA coming from SX/SY

plus the usual pull-up current. Therefore the external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/

SY as a function of junction temperature are shown in Figure 10, and the equivalent circuit at the SX/SY interface is shown in Figure 4.

[2]

Valid over temperature for VCC ≤ 5 V. At higher VCC, this current may increase to maximum -20 μA at VCC = 15 V.

[3]

The input logic threshold is independent of the supply voltage.

[4]

The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for VSX output LOW will always exceed the maximum VSX

input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute

levels allow a small probability, the LOW from one SX output is recognized by an SX input of another PCA9600, this has no consequences for normal

applications. In any design the SX pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise

and would not support all I2C-bus operating modes.

[5]

The fall time of VTX from 5 V to 2.5 V in the test is approximately 10 ns.

The fall time of VSX from 5 V to 2.5 V in the test is approximately 20 ns.

The rise time of VTX from 0 V to 2.5 V in the test is approximately 15 ns.

The rise time of VSX from 0.7 V to 2.5 V in the test is approximately 25 ns.

002aac838

VCC

≤ 1 mA

SX (SY)

Vref

Figure 4. Equivalent circuit at SX/SY

PCA9600

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 6.1 — 20 December 2021

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