NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

PCA9600

SCL

RX

TX

002aac851

SX

VCC

TY

RY

SY

R2

R2

C2

C2

I2C-BUS

MASTER

SDA

VCC1

GND

R1 R1

BAT54A

cable

propagation

delay ≈ 5 ns/m

BAT54A

R1 R1

PCA9600

RX

TX

TY

RY

VCC

SX

SY

R2

R2

SCL

SDA

VCC2

GND

I2C-BUS

SLAVE(S)

C2

C2

+V cable drive

Figure 14. Driving ribbon or flat telephone cables

Refer to Figure 14.

Set master

nominal SCL

VCC1

(V)

+V

cable

(V)

VCC2

(V)

R1

(Ω)

R2

(kΩ)

C2

(pF)

Cable

length

(m)

Cable

capacitance

Cable

delay

HIGH

period

(ns)

LOW

period

(ns)

Effective

bus

clock

speed

(kHz)

Max. slave

response

delay

5

12

5

750 2.2

400 250

n/a (delay

based)

1.25 μs 600

3 850

125

normal

specification

400 kHz parts

5

12

5

750 2.2

220 100

n/a (delay

based)

500 ns

600

2 450

195

normal

specification

400 kHz parts

3.3

5

3.3

330 1

220 25

1 nF

125 ns

260

770

620

meets Fm+

specification

3.3

5

3.3

330 1

100 3

120 pF

15 ns

260

720

690

meets Fm+

specification

Table 7. Examples of bus capability

For more examples of faster alternatives for driving over longer cables such as Cat5

communication cable, see AN10658. Communication at 1 MHz is possible over short

cables and > 400 kHz is possible over 50 m of cable.

PCA9600

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 6.1 — 20 December 2021

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