数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ISO7240CFDWR 数据表(PDF) 8 Page - Texas Instruments

Click here to check the latest version.
部件名 ISO7240CFDWR
功能描述  QUAD DIGITAL ISOLATOR WITH SELECTABLE FAILSAFE OUTPUT
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

ISO7240CFDWR 数据表(HTML) 8 Page - Texas Instruments

Back Button ISO7240CFDWR Datasheet HTML 4Page - Texas Instruments ISO7240CFDWR Datasheet HTML 5Page - Texas Instruments ISO7240CFDWR Datasheet HTML 6Page - Texas Instruments ISO7240CFDWR Datasheet HTML 7Page - Texas Instruments ISO7240CFDWR Datasheet HTML 8Page - Texas Instruments ISO7240CFDWR Datasheet HTML 9Page - Texas Instruments ISO7240CFDWR Datasheet HTML 10Page - Texas Instruments ISO7240CFDWR Datasheet HTML 11Page - Texas Instruments ISO7240CFDWR Datasheet HTML 12Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 16 page
background image
VCM
IN
OUT
GND1
NOTEB
S1
V
orV
OH
OL
V
1
CC
V
2
CC
C=0.1 F±1%
m
C=0.1 F±1%
m
GND2
Pass-failcriteria:
Outputmust
remainstable
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
DEVICE I/O SCHEMATICS
W
1 M
VCC2
500 W
VCC2
EN
OUT
8
13
W
W
V
CC2
OUTPUT
IN
W
V
CC1
1 M
V
CC1
500 W
INPUT
DISABLE
CTRL
W
1 M
VCC2
500 W
EN
V
CC 2
V
CC 2
ISO7240CF
SLLS869B – SEPTEMBER 2007 – REVISED APRIL 2008 ................................................................................................................................................ www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A.
The input pulse is supplied by a generator having the following characteristics: PRR
≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
7.7
mm
Minimum external tracking
Shortest terminal-to-terminal distance across the
L(I02)
8.1
mm
(Creepage)
package surface
Minimum Internal Gap (Internal
Distance through the insulation
0.008
mm
Clearance)
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
>1012
RIO
Isolation resistance
TA < 100°C
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
>1011
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
1
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
1
pF
8
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s) :ISO7240CF



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com