M28C16A datasheet(4/19 Pages) STMICROELECTRONICS

4 / 19 page

AI01520

ADDRESS

LATCH

A6-A10

(Page Address)

CONTROL LOGIC

64K ARRAY

ADDRESS

LATCH

A0-A5

Y DECODE

VPP GEN

RESET

SENSE AND DATA LATCH

I/O BUFFERS

PAGE LOAD

TIMER STATUS

TOGGLE BIT

DATA POLLING

DQ0-DQ7

Figure 3. Block Diagram

Write

Write operations are initiated when both W and E

are low and G is high.The M28C16A/17Asupports

both E and W controlled write cycles. The Address

is latched by the falling edge of E or W which ever

occurs last and the Data on the rising edge of E or

W which ever occurs first. Once initiated the write

operation is internally timed until completion.

Page Write

Page write allows up to 32 bytes to be consecu-

tively latched into the memory prior to initiating a

DQ7

DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

PLTS Hi-Z

Hi-Z

Figure 4. Status Bit Assignment

DP = Data Polling

TB = Toggle Bit

PLTS = Page Load Timer Status

programming cycle. All bytes must be located in a

single page address, that is A5 - A10 must be the

same for all bytes. The page write can be initiated

during any byte write operation.

Following the first byte write instruction the host

may send another address and data up to a maxi-

mum of tWHWH after the rising edge of E or W which

ever occurs first. If a transition of E or W is not

detected within tWHWH, the internal programming

cycle will start.

Microcontroller Control Interface

The M28C16A/17A provides two write operation

status bits and one status pin that can be used to

minimize the system write cycle. These signals are

available on the I/O port bits DQ7 or DQ6 of the

memory during programming cycle only, or as the

RB signal on a separate pin.

Data Polling bit (DQ7). During the internal write

cycle, any attempt to read the last byte written will

produce on DQ7 the complementary value of the

previously latched bit. Once the write cycle is fin-

ished the true logic value appears on DQ7 in the

read cycle.

OPERATION (cont’d)

4/19

M28C16A, M28C17A

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