M29F010B datasheet(9/20 Pages) STMICROELECTRONICS

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M29F010B

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the blocks being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Table 7. Status Register Bits

Note: Unspecified data bits should be ignored.

Operation

Address

DQ7

DQ6

DQ5

DQ3

DQ2

Program

Any Address

DQ7

Toggle

–

Program During Erase Suspend

Any Address

DQ7

Toggle

–

Program Error

Any Address

DQ7

Toggle

–

Chip Erase

Any Address

Toggle

Block Erase before timeout

Erasing Block

Toggle

Non-Erasing Block

Toggle

No Toggle

Block Erase

Erasing Block

Toggle

Non-Erasing Block

Toggle

No Toggle

Erase Suspend

Erasing Block

No Toggle

–

Toggle

Non-Erasing Block

Data read as normal

Erase Error

Good Block Address

Toggle

No Toggle

Faulty Block Address

Toggle

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