M29F016B datasheet(5/22 Pages) STMICROELECTRONICS

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M29F016B

Table 4. Bus Operations

Note: X = VIL or VIH.

Operation

Address Inpu ts

Data

Inputs/Outpu ts

Bus Read

VIL

VIH

Cell Address

Data Output

Bus Write

VIL

VIH

VIL

Command Address

Data Input

Output Disable

VIH

XHi-Z

Standby

VIH

Hi-Z

Read Manufacturer

Code

VIL

VIH

A0 = VIL,A1 = VIL,A9 = VID,

Others VIL or VIH

20h

Read Device Code

VIL

VIH

A0 = VIH,A1 = VIL,A9 = VID,

Others VIL or VIH

ADh

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 14 and Figure

11, Reset/Temporary Unprotect AC Characteris-

tics.

During Program or Erase operations Ready/Busy

is Low, VOL. Ready/Busy will remain Low during

Read/Reset commands or Hardware Resets until

the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1

µF capacitor should be connected between

the VCC Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, ICC4.

VSS Ground. The VSS Ground is the reference for

all voltage measurements.

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Table 4, Bus Operations, for a summary. Typically

glitches of less than 5ns on Chip Enable or Write

Enable are ignored by the memory and do not af-

fect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs/Outputs will output the

value, see Figure 8, Read Mode AC Waveforms,

and Table 11, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, VIH, during the whole Bus

Write operation. See Figures 9 and 10, Write AC

Waveforms, and Tables 12 and 13, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is re-

duced to the Standby level.

When Chip Enable is at VIH the Supply Current is

reduced to the TTL Standby Supply Current, ICC2.

To further reduce the Supply Current to the CMOS

Standby Supply Current, ICC3, Chip Enable should

be held within VCC ± 0.2V. For Standby current

levels see Table 10, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC4, for Program or Erase operations un-

til the operation completes.

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