M29F512B

2/16

Figure 2A. TSOPConnections

A1

A0

DQ0

A7

A4

A3

A2

A6

A5

A13

A10

A8

A9

DQ7

A14

A11

G

E

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

NC

W

NC

A12

NC

VCC

A15

AI02741

M29F512B

8

1

9

16

17

24

25

32

VSS

Table 1. Signal Names

A0-A15

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

E

Chip Enable

G

Output Enable

W

Write Enable

Supply Voltage

Ground

NC

Not Connected Internally

quired to update the memory contents. The end of

a program or erase operation can be detected and

any error conditions identified. The command set

required to control the memory is consistent with

JEDEC standards.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP32 (8 x 14mm) and

PLCC32 packages. Access times of 45ns and

70ns are available. The memory is supplied with

all the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A15). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Figure 2B. PLCC Connections

AI02930

A13

A10

17

A1

A0

DQ0

A7

A4

A3

A2

A6

A5

9

A8

1

A9

DQ7

A14

32

M29F512B

A11

G

E

25

SUMMARY DESCRIPTION

The M29F512B is a 512 Kbit (64Kb x8) non-vola-

tile memory that can be read, erased and repro-

grammed. These operations can be performed

using a single 5V supply. On power-up the memo-

ry defaults to its Read mode where it can be read

in the same way as a ROM or EPROM.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-