M29W040 datasheet(14/31 Pages) STMICROELECTRONICS

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Symbol

Alt

Parameter

M29W040

Unit

-150

-200

VCC = 2.7V to 3.6V

Min

Max

Min

Max

tAVAV

tWC

Address Valid to Next Address Valid

150

200

tELWL

tCS

Chip Enable Low to Write Enable Low

tWLWH

tWP

Write Enable Low to Write Enable High

tDVWH

tDS

Input Valid to Write Enable High

tWHDX

tDH

Write Enable High to Input Transition

tWHEH

tCH

Write Enable High to Chip Enable High

tWHWL

tWPH Write Enable High to Write Enable Low

tAVWL

tAS

Address Valid to Write Enable Low

tWLAX

tAH

Write Enable Low to Address Transition

tGHWL

Output Enable High to Write Enable Low

tVCHEL

tVCS

VCC High to Chip Enable Low

µs

tWHQV1

(1)

Write Enable High to Output Valid (Program)

µs

tWHQV2

(1)

Write Enable High to Output Valid

(Block Erase)

1.5

sec

tWHGL

tOEH

Write Enable High to Output Enable Low

Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV =tWHQ7V +tQ7VQV.

Table 13B. Write AC Characteristics, Write Enable Controlled

(TA = 0 to 70

°C, –20 to 85°C or –40 to 85°C)

Block Erase (BE) instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 5555h

on third cycle after the two coded cycles. The Block

Erase Confirm command 30h is written on sixth

cycle after another two coded cycles. During the

input of the second command an address within

the block to be erased is given and latched into the

memory. Additional Block Erase confirm com-

mands and block addresses can be written sub-

sequently to erase other blocks in parallel, without

further coded cycles. The erase will start after the

Erase timeout period (see Erase Timer Bit DQ3

description). Thus, additional Block Erase com-

mands must be given within this delay. The input of

a newBlock Erase command will restart the timeout

period. The status of the internal timer can be

monitored through the level of DQ3, if DQ3 is ’0’ the

Block Erase Command has been given and the

timeout is running, if DQ3 is ’1’, the timeout has

expired and the P/E.C is erasing the block(s).

During Erase timeout, any command different from

30h will abort the instruction and reset the device

to read array mode. It is not necessary to program

the block with 00h as the P/E.C. will do this auto-

matically before erasing to FFh. Read operations

after the sixth rising edge of W or E output the

status register bits.

During the execution of the erase by the P/E.C.,the

memory accepts only the ES (Erase Suspend) and

RST (Reset) instructions. Data Polling bit DQ7

returns ’0’ while the erasure is in progress and ’1’

when it has completed.The Toggle Bit DQ6 toggles

during the erase operation. It stops when erase is

completed. After completion the Status Register

bit DQ5 returns ’1’ if there has been an Erase

Failure because erasure has not completed even

after the maximum number of erase cycles have

been executed. In this case, it will be necessary to

input a Reset (RST) to the command interface in

order to reset the P/E.C.

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