During a very long internal operation (device initiali-

zation after RESET going high or execution of in-

struction 6) a new set of data bytes with a valid op-

code is accepted while a wrong code is rejected. At

the end of the current routine execution takes place

in the same way as described before.

At the end of an instruction it is normally recom-

mended to read one or both registers. To exploit in-

struction 6, however, it is mandatory to read register

OR2. This is because instruction 6, used between

other short instructions of type 1 to 5, must have pri-

ority and can be enabled only after the short instruc-

tions have been completed. Instruction 6 normally

has a long process and a special flow which is de-

scribed below.

First a not-all-zero mask is stored in the ”expected

messages” register and in another ”background”

register. This operation starts the second phase of

instruction 6 which is called ”channel 0 extraction”

and is repeated at the beginning of any new time

frame.At the beginningof the time frame a new copy

of activated channels to be extracted is made from

the ”background register” and put in the ”expected

messages” register. In addition the latter register is

modified to indicate the exact number of messages

that have arrived. The term messages covers any

input 0 channeldata with starting sequencedifferent

from the label 01. So using this label the number of

expected messages can be reduced to correspond

to the number of effective messages. If and only if

the residual number is different from zero will the de-

vice start the extraction protocol at the end of the

current routine.

The procedureis as follows : the DR outputis pulsed

low as a two cycle interrupt request and OR2 is

loaded with the total number of active channels to

be extracted.

The transfer of OR2 content to the microprocessor

continues the extraction which consists of repeated

steps of OR1 and OR2 loading, indicating respec-

tively the message and the incoming bus number.

Reading the registers in the order OR1, OR2 must

be continued until completion or until the time frame

runs out.

With a new time frame a new extraction process be-

gins, resuming the copy operation from the back-

ground register.

During extraction the active channels are scanned

from the highest to the lowest number (from 7 to 0).

While extraction is being carried out the time interval

requirements between active rising edges of RD are

details are given in the following tables.

INSTRUCTION TABLES

The most significant digits of OR2 A7, A6, A5 are a

copy of the PCM selected output bus ; the least sig-

nificant digits of OR2 are the opcode, C8 is the con-

trol bit. In any case parentheses() define actual reg-

ister content.

INSTRUCTION 1: CHANNEL CONNECTION

Control Signals

Data Bus

Notes

Match C/D

CS

WR

RD

D7

D6

D5

D4

D3

D2

D1

D0

X

0

0

0

1

XXXXX

Bi2

Bi1

Bi0

1

X

0

0

0

1

X

X

X

Ci4

Ci3

Ci2

Ci1

Ci0

2

x

0

0

0

1

XXXXX

Bo2 Bo1 Bo0 3

X

0

0

0

1

X

X

X

Co4 Co3 Co2 Co1 Co0 4th Data Byte: selected output channel.

yes/no

1

0

0

1

XXXX

0001

Instruction Opcode

yes

0

0

1

0

C7

(1

(Bi2

C6

1

Bi1

C5

1

Bi0

C4

1

Ci4

C3

1

Ci3

C2

1

Ci2

C1

1

Ci1

C0

1)

Ci0)

OR1: CM content copy, that is,

for mismatch condition,

for match condition

yes

1

0

1

0

A7

(Bo2

(Bo2

A6

Bo1

Bo1

A5

Bo0

Bo0

C8

1

0

0

0

0

0

0

0

0

0

0

1

1)

1)

OR2: that is,

for mismatch condition

for match condition

M3488

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