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M34A02

can be calculated). In most applications, though,

this method of synchronization is not employed,

and so the pull-up resistor is not necessary,

provided that the bus master has a push-pull

(rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in

or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open

collector signals on the bus. A pull up resistor must

(Figure 3 indicates how the value of the pull-up

resistor can be calculated).

Chip Enable (E0, E1, E2)

These input signals are used to set the value that

is to be looked for on the three least significant bits

(b3, b2, b1) of the 7-bit Device Select Code. These

the Device Select Code.

Write Control (WC)

This input signal is useful for protecting the entire

contents of the memory from inadvertent erase

and

write

operations.

Write

operations

are

disabled to the entire memory array when Write

Control (WC) is held High. When unconnected, the

operations are allowed.

When Write Control (WC) is held High, Device

Select and Address bytes are acknowledged,

Data bytes are

DEVICE OPERATION

The device supports the ACR Serial Bus protocol.

This is summarized in Figure 4. Any device that

sends data on to the bus is defined to be a

transmitter, and any device that reads the data to

be a receiver. The device that controls the data

transfer is known as the bus master, and the other

as the slave device. A data transfer can only be

initiated by the bus master, which will also provide

the serial clock for synchronization. The device is

always a slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of the SDA line

while the clock SCL is stable in the High state. A

Stop

condition

terminates

communication

between the device and the bus master. A Stop

condition at the end of a Read command, provided

that it is followed by NoAck, forces the device into

its Stand-by mode. A Stop condition at the end of

a Write command triggers the internal EEPROM

Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a

successful byte transfer. The bus transmitter,

whether it be bus master or slave device, releases

Serial Data (SDA) after sending eight bits of data.

Serial Data (SDA) Low to acknowledge the receipt

of the eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

AI01665

VCC

CBUS

SDA

RL

MASTER

RL

SCL

CBUS

100

0

4

8

12

16

20

CBUS (pF)

10

1000

fc = 400kHz

fc = 100kHz