M36DR232A datasheet(22/46 Pages) STMICROELECTRONICS

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M36D232A, M36DR232B

22/46

SRAM COMPONENT

Device Operations

The following operations can be performed using

the appropriate bus cycles: Read Array, Write Ar-

ray, Output Disable, Power Down (see Table 3).

Read. Read operations are used to output the

contents of the SRAM Array. The SRAM is in Read

mode whenever Write Enable (WS)is at VIH with

Output Enable (GS)at VIL, and both Chip Enables

(E1S and E2S) and UBS,LBS combinations are

asserted.

Valid data will be available at the output pins within

tAVQV after the last stable address, providing GS is

Low, E1S is Low and E2S is High. If Chip Enable

or Output Enable access times are not met, data

access will be measured from the limiting parame-

ter (tE1LQV,tE2HQV,or tGLQV) rather than the ad-

dress. Data out may be indeterminate at tE1LQX,

tE2HQX and tGLQX, but data lines will always be val-

id at tAVQV (see Table 31, Figures 16 and 17).

Write. Write operations are used to write data in

the SRAM. The SRAM is in Write mode whenever

the WS and E1S pins are at VIL, with E2S at VIH.

Either the Chip Enable inputs (E1S and E2S) or

the Write Enable input (WS) must be de-asserted

during address transitions for subsequent write cy-

cles. Write begins with the concurrence of both

Chip Enables being active with WS at VIL.AWrite

begins at the latest transition among E1S going to

VIL, E2S goingtoVIH and WS going to VIL. There-

fore, address setup time is referenced to Write En-

able and both Chip Enables as tAVWL,tAVE1L and

tAVE2H respectively, and is determined by the latter

occurring edge. The Write cycle can be terminated

by therisingedgeof E1S, the rising edge of WS or

the falling edge of E2S, whichever occurs first.

If the Output is enabled (E1S=VIL,E2S=VIH and

GS=VIL), then WS will return the outputs to high

impedance within tWLQZ of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. Data input must be valid for tDVWH

before the rising edge of Write Enable, or for

tDVE1H before the rising edge of E1S or for tDVE2L

before the falling edge of E2S, whichever occurs

first, and remain valid for tWHDX,tE1HAX or tE2LAX

(see Table 32, Figure 19, 21, 23).

Standby/Power-Down. The SRAM chip has a

Chip Enable power-down feature which invokes

an automatic standby mode (see Table 31, Figure

18) whenever either Chip Enable is de-asserted

(E1S=VIH or E2S=VIL).

Data Retention

The SRAM data retention performances as VCCS

go down to VDR are described in Table 33 and Fig-

ure 23, 24. In E1S controlled data retention mode,

minimum standby current mode is entered when

E1S

≥ VCCS – 0.2V

and

E2S

≤ 0.2V

E2S

≥ VCCS – 0.2V. In E2S controlled data reten-

tion mode, minimum standby current mode is en-

tered when E2S

≤ 0.2V.

Output Disable. The data outputs are high im-

pedance when the Output Enable (GS)isat VIH

with Write Enable (WS)at VIH.

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