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MSC8103RM/D 数据表(PDF) 57 Page - Freescale Semiconductor, Inc |
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MSC8103RM/D 数据表(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 104 page ![]() AC Timings MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 2-17 Figure 2-10. Bus Signal Timing DLLIN AACK/ARTRY/TA/TEA/DBG/BG/BR Data bus inputs—normal mode PUPMWAIT/IRQn input PSDVAL/TEA/TA outputs Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL/BADDR[27–31] outputs Data bus outputs All other normal mode outputs 11 10 10 10 12 15 31 32 33a 36 DP outputs 33b Memory controller/ALE signals 34 Data bus inputs—ECC and parity modes 10 13 AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals 35 DP inputs 14 Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs 16 PSDVAL/ABB/DBB/TS inputs |
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