M48Z129Y, M48Z129V

2/13

Figure 2A. DIP Pin Connections

A1

A0

DQ0

A7

A4

A3

A2

A6

A5

A13

A10

A8

A9

DQ7

A15

A11

G

E

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A16

RST

VCC

AI02310

M48Z129Y

M48Z129V

10

1

2

5

6

7

8

9

11

12

13

14

15

16

30

29

26

25

24

23

22

21

20

19

18

17

A12

A14

W

BL

3

4

28

27

32

31

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section

of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect

reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

0 to 70

°C

–40 to 70

°C

Temperature Under Bias

–10 to 70

°C

(2)

Lead Solder Temperature for 10 seconds

260

°C

Input or Output Voltages

V

Supply Voltage

M48Z129Y

M48Z129V

–0.3 to 7.0

–0.3 to 4.6

V

DESCRIPTION

The M48Z129Y/V ZEROPOWER SRAM is a

1,048,576 bit non-volatile static RAM organized as

131,072 words by 8 bits. The device combines an

internal lithium battery, a CMOS SRAM and a con-

trol circuit in a plastic 32 pin DIP Module. The

M48Z129Y/V directly replaces industry standard

128K x 8 SRAM. It also provides the non-volatility

of FLASH without any requirement for special

write timing or limitations on the number of writes

that can be performed.

The M48Z129Y/V also has its own Power-Fail De-

tect circuit. This control circuitry constantly moni-

tors the supply voltage for an out of tolerance

write protects the SRAM, providing data security in

the midst of unpredictable system operation. As

es to the battery, maintaining data until valid power

is restored.

READ MODE

The M48Z129Y/V is in the Read Mode whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the 17 Ad-

dress Inputs defines which one of the 131,072

bytes of data is to be accessed. Valid data will be

dress Access Time) after the last address input

signal is stable, providing the E and G access

times are also satisfied. If the E and G access

times are not met, valid data will be available after

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

puts are changed while E and G remain active,

Data Hold Time) but will go indeterminate until the

next Address Access.