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M48Z129Y, M48Z129V

WRITE MODE

The M48Z129Y/V is in the Write Mode whenever

W (Write Enable) and E (Chip Enable) are active.

The start of a write is referenced from the latter oc-

curring falling edge of W or E. A write is terminat-

ed by the earlier rising edge of W or E. The

addresses must be held valid throughout the cycle.

to the initiation of another read or write cycle.

should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G a low on W

DATA RETENTION MODE

as a conventional BYTEWIDE static RAM. Should

the supply voltage decay, the RAM will automati-

outputs become high impedance and all inputs are

treated as “don’t care”.

2. See Table 7 for details.

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.5V to 5.5V

(M48Z129Y)

or

3.0V to 3.6V

(M48Z129V)

X

X

High Z

Standby

Write

X

Active

Read

Active

Read

High Z

Active

Deselect

(2)

X

X

X

High Z

CMOS Standby

Deselect

X

X

X

High Z

Battery Back-up Mode

Figure 3. Block Diagram

AI03608

RST

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

131,072 x 8

SRAM ARRAY

A0-A16

DQ0-DQ7

E

W

G

POWER

VCC

BL

E

INTERNAL

BATTERY