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M48Z30 数据表(PDF) 2 Page - STMicroelectronics |
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M48Z30 数据表(HTML) 2 Page - STMicroelectronics |
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2 / 12 page ![]() Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode. Symbol Parameter Value Unit TA Ambient Operating Temperature 0 to 70 °C TSTG Storage Temperature (VCC Off) –40 to 70 °C TBIAS Temperature Under Bias –10 to 70 °C TSLD Lead Soldering Temperature for 10 seconds 260 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V Table 2. Absolute Maximum Ratings Figure 2. DIP Pin Connections RAM directly replaces industry standard SRAMs. It also fits into many EPROM and EEPROM sockets, providing the nonvolatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The M48Z30/30Y has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system op- erations brought on by low VCC.As VCC falls below approximately3V, the control circuitry connectsthe battery which sustains data until valid power re- turns. READ MODE The M48Z30/30Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through ac- cess of data from eight of 262,144 locations in the static storage array. Thus, the unique address Mode VCC E G W DQ0-DQ7 Power Deselect 4.75V to 5.5V or 4.5V to 5.5V VIH X X High Z Standby Write VIL XVIL DIN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect VSO to VPFD (min) X X X High Z CMOS Standby Deselect ≤ VSO X X X High Z Battery Back-up Mode Table 3. Operating Modes Note:X = VIH or VIL DESCRIPTION (cont’d) 2/12 M48Z30, M48Z30Y |
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