M48Z35AV datasheet(8/16 Pages) STMICROELECTRONICS

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M48Z35AY, M48Z35AV

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Table 10. Write Mode AC Characteristics

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)

Note: 1. CL = 5pF (see Figure 4).

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Symbol

Parameter

M48Z35AY

M48Z35AV

Unit

-70

-100

Min

Max

Min

Max

tAVAV

Write Cycle Time

100

tAVWL

Address Valid to Write Enable Low

tAVEL

Address Valid to Chip Enable Low

tWLWH

Write Enable Pulse Width

tELEH

Chip Enable Low to Chip Enable High

tWHAX

Write Enable High to Address Transition

tEHAX

Chip Enable High to Address Transition

tDVWH

Input Valid to Write Enable High

tDVEH

Input Valid to Chip Enable High

tWHDX

Write Enable High to Input Transition

tEHDX

Chip Enable High to Input Transition

tWLQZ

(1, 2)

Write Enable Low to Output Hi-Z

tAVWH

Address Valid to Write Enable High

tAVEH

Address Valid to Chip Enable High

tWHQX

(1, 2)

Write Enable High to Output Transition

DATA RETENTION MODE

With valid VCC applied, the M48Z35AY/35AV op-

erates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM

will automatically power-fail deselect, write pro-

tecting itself when VCC falls within the VPFD(max),

VPFD(min) window. All outputs become high im-

pedance, and all inputs are treated as "don't care."

Note: A power failure during a write cycle may

corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's con-

tent. At voltages below VPFD(min), the user can be

assured the memory will be in a write protected

state, provided the VCC fall time is not less than tF.

The M48Z35AY/35AV may respond to transient

noise spikes on VCC that reach into the deselect

window during the time the device is sampling

VCC. Therefore, decoupling of the power supply

lines is recommended.

When VCC drops below VSO, the control circuit

switches power to the internal battery which pre-

serves data. The internal button cell will maintain

data in the M48Z35AY/35AV for an accumulated

period of at least 10 years (at 25°C) when VCC is

less than VSO.

As system power returns and VCC rises above

VSO, the battery is disconnected, and the power

supply is switched to external VCC. Write protec-

tion continues until VCC reaches VPFD(min) plus

tREC(min). Normal RAM operation can resume

tREC after VCC exceeds VPFD(max).

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