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April 2000

M48Z35AY

M48Z35AV

s

INTEGRATED ULTRA LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and

BATTERY

s

READ CYCLE TIME EQUALS WRITE CYCLE

TIME

s

BATTERY LOW FLAG (BOK)

s

AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

s

WRITE PROTECT VOLTAGES

– M48Z35AY: 4.20V

– M48Z35AV: 2.7V

s

SELF-CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

s

PACKAGING INCLUDES a 28-LEAD SOIC and

(to be Ordered Separately)

s

SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which

CONTAINS the BATTERY and CRYSTAL

s

PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32K x8 SRAMs

DESCRIPTION

32 Kbit x8 non-volatile static RAM that integrates

power-fail deselect circuitry and battery control

logic on a single die. The monolithic chip is avail-

able in two special packages to provide a highly in-

tegrated battery backed-up memory solution.

Figure 1. Logic Diagram

AI02781B

15

A0-A14

W

DQ0-DQ7

VCC

M48Z35AY

M48Z35AV

G

VSS

8

E

Table 1. Signal Names

A0-A14

Address Inputs

DQ0-DQ7

Data Inputs / Outputs

E

Chip Enable

G

Output Enable

W

Write Enable

Supply Voltage

Ground

28

1

28

1

SOH28 (MH)

SNAPHAT (SH)

Battery

PCDIP28 (PC)

Battery CAPHAT