M50LPW040N datasheet(7/36 Pages) STMICROELECTRONICS

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M50LPW040

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command

Interface or Low Pin Count Registers. A valid Bus

Read operation starts when Input Communication

Frame, LFRAME, is Low, VIL, as Clock rises and

the correct Start cycle is on LAD0-LAD3. On the

following clock cycles the Host will send the Cycle

Type + Dir, Address and other control bits on

LAD0-LAD3. The memory responds by outputting

Sync data until the wait-states have elapsed

followed by Data0-Data3 and Data4-Data7.

Refer to Table 6, and Figure 5, for a description of

the Field definitions for each clock cycle of the

transfer. See Table 22, LPC Interface AC Signal

Timing Characteristics and Figure 10, LPC Inter-

face AC Signal Timing Waveforms, for details on

the timings of the signals.

Bus Write. Bus Write operations write to the

Command Interface or Low Pin Count Registers. A

valid Bus Write operation starts when Input

Communication Frame, LFRAME, is Low, VIL, as

Clock rises and the correct Start cycle is on LAD0-

LAD3. On the following Clock cycles the Host will

send the Cycle Type + Dir, Address, other control

bits, Data0-Data3 and Data4-Data7 on LAD0-

LAD3. The memory outputs Sync data until the

wait-states have elapsed.

Refer to Table 7, LPC Bus Write Field Definitions,

and Figure 6, LPC Bus Write Waveforms, for a

description of the Field definitions for each clock

cycle of the transfer. See Table 22, LPC Interface

AC Signal Timing Characteristics and Figure 10,

LPC Interface AC Signal Timing Waveforms, for

details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when LFRAME is driven Low,

VIL, during the bus operation; the memory will tri-

state

the

Input/Output

Communication

pins,

LAD0-LAD3.

Note that, during a Bus Write operation, the

Command

Interface

starts

executing

the

command as soon as the data is fully received; a

Bus Abort during the final TAR cycles is not

guaranteed to abort the command; the bus,

however, will be released immediately.

Standby. When LFRAME is High, VIH, the

memory is put into Standby mode where LAD0-

LAD3 are put into a high-impedance state and the

Supply Current is reduced to the Standby level,

ICC1.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

Reset, INIT, is Low, VIL. RP or INIT must be held

Low, VIL, for tPLPH. The memory resets to Read

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset, see Table 15. If RP or

INIT goes Low, VIL, during a Program or Erase

operation, the operation is aborted and the

memory cells affected no longer contain valid

data; the memory can take up to tPLRH to abort a

Program or Erase operation.

Block Protection. Block

Protection

can

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Table 5. Block Addresses

Note: For A19 value, refer to Table 2.

Size

(Kbytes)

Address Range

Block

Number

Block Type

70000h-7FFFFh

Top Block

60000h-6FFFFh

Main Block

50000h-5FFFFh

Main Block

40000h-4FFFFh

Main Block

30000h-3FFFFh

Main Block

20000h-2FFFFh

Main Block

10000h-1FFFFh

Main Block

00000h-0FFFFh

Main Block

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