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M50LPW041

Clock rises and the correct Start cycle is on LAD0-

LAD3. On the following Clock cycles the Host will

send the Cycle Type + Dir, Address, other control

bits, Data0-Data3 and Data4-Data7 on LAD0-

LAD3. The memory outputs Sync data until the

wait-states have elapsed.

Refer to Table 8, LPC Bus Write Field Definitions,

and Figure 6, LPC Bus Write Waveforms, for a

description of the Field definitions for each clock

cycle of the transfer. See Table 23, LPC Interface

AC Signal Timing Characteristics and Figure 10,

LPC Interface AC Signal Timing Waveforms, for

details on the timings of the signals.

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when LFRAME is driven Low,

state

the

Input/Output

Communication

pins,

LAD0-LAD3.

Note that, during a Bus Write operation, the

Command

Interface

starts

executing

the

command as soon as the data is fully received; a

Bus Abort during the final TAR cycles is not

guaranteed to abort the command; the bus,

however, will be released immediately.

memory is put into Standby mode where LAD0-

LAD3 are put into a high-impedance state and the

Supply Current is reduced to the Standby level,

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset, see Table 16. If RP or

operation, the operation is aborted and the

memory cells affected no longer contain valid

Program or Erase operation.

Block Protection. Block

Protection

can

be

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux)

Interface has a more traditional style interface.

The signals consist of a multiplexed address

signals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional

signal, RP, can be used to reset the memory.

The Address/Address Multiplexed (A/A Mux)

Interface

is

included

for

use

by

Flash

Programming

equipment

for

faster

factory

programming. Only a subset of the features

available to the Low Pin Count (LPC) Interface are

available; these include all the Commands but

exclude the Security features and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface

is

selected

all

the

blocks

are

unprotected. It is not possible to protect any blocks

through this interface.

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

and for less than 20ns during transitions.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature (Temperature Range Option 1)

0 to 70

°C

Temperature Under Bias

–50 to 125

°C

Storage Temperature

–65 to 150

°C

(2)

Input or Output Voltage

V

Supply Voltage

–0.6 to 4

V

Program Voltage

–0.6 to 13

V