M50LPW041K datasheet(15/37 Pages) STMICROELECTRONICS

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M50LPW041

Table 14. Status Register Bits

Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

Operation

Bit 7

Bit 6

Bit 5

Bit 4

Bit 2

Bit 1

Program active

X(1)

0000

Program suspended

X(1)

0010

Program completed successfully

X(1)

0000

Program failure due to Block Protection (LPC Interface only)

X(1)

0001

Program failure due to cell failure

X(1)

0100

Erase active

0000

Block Erase suspended

0000

Erase completed successfully

0000

Block Erase failure due to Block Protection (LPC Interface only)

0001

Erase failure due to failed cell(s)

1000

Once the Program Status bit is set to ‘1’ it can only

be reset to ‘0’ by a Clear Status Register com-

mand or a hardware reset. If it is set to ‘1’ it should

be reset before a new Program or Erase command

is issued, otherwise the new command will appear

to fail.

Reserved (Bit 3). This status bit is reserved for

future use. Its value should be masked out when-

ever the status register is read.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the

Program/Erase Controller is active or has complet-

ed its operation; when the bit is ‘1’ a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns to

‘0’.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if the Pro-

gram or Block Erase operation has tried to modify

the contents of a protected block. When the Block

Protection Status bit is to ‘0’ no Program or Block

Erase operations have been attempted to protect-

ed blocks since the last Clear Status Register

command or hardware reset; when the Block Pro-

tection Status bit is ‘1’ a Program or Block Erase

operation has been attempted on a protected

block.

Once it is set to ‘1’ the Block Protection Status bit

can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If it is set to ‘1’ it

should be reset before a new Program or Block

Erase command is issued, otherwise the new

command will appear to fail.

Using the A/A Mux Interface the Block Protection

Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value should be masked.

LOW PIN COUNT (LPC) INTERFACE

CONFIGURATION REGISTERS

When the Low Pin Count Interface is selected sev-

eral additional registers can be accessed. These

registers control the protection status of the Blocks

and read the General Purpose Input pins. See Ta-

ble 15 for an example of the Register Configura-

tion map, valid for the boot memory, that is, ID0-

ID3 can be left floating or driven Low, VIL.

Lock Registers

The Lock Registers control the protection status of

the Blocks. Each Block has its own Lock Register.

Three bits within each Lock Register control the

protection of each block, the Write Lock Bit, the

Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,

though care should be taken when writing as, once

the Lock Down Bit is set, ‘1’, further modifications

to the Lock Register cannot be made until cleared,

to ‘0’, by a reset or power-up.

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