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M50LPW080 数据表(PDF) 16 Page - STMicroelectronics |
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M50LPW080 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 44 page ![]() M50LPW080 16/44 COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. After power-up or a Reset operation the memory enters Read mode. The commands are summarized in Table 10.. The following text descriptions should be read in con- junction with Table 10.. Read Memory Array Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is is- sued the memory remains in Read mode until an- other command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes. Read Status Register Command. The Read Status Register command is used to read the Sta- tus Register. One Bus Write cycle is required to is- sue the Read Status Register command. Once the command is issued subsequent Bus Read opera- tions read the Status Register until another com- mand is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Elec- tronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until an- other command is issued. After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 9.. Table 9. Read Electronic Signature Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write opera- tions are required to issue the command; the sec- ond Bus Write cycle latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. Once the command is is- sued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the address falls in a protected block then the Program operation will abort, the data in the mem- ory array will not be changed and the Status Reg- ister will output the error. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 15.. Note that the Program command cannot change a bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 17. for a suggested flowchart on using the Program command. Quadruple Byte Program Command. The Qua- druple Byte Program Command can be only used in A/A Mux mode to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A10. Pro- gramming should not be attempted when VPP is not at VPPH. The operation can also be executed if VPP is below VPPH, but result could be uncertain. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend com- mand. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 15.. Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and at- tempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 18. for a suggested flowchart on using the Quadruple Byte Program command. Code Address Data Manufacturer Code 00000h 20h Device Code 00001h 2Fh |
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