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M5482 数据表(PDF) 3 Page - STMicroelectronics |
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M5482 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 6 page ![]() STATIC ELECTRICAL CHARACTERISTICS (Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V,unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Supply Voltage 4.75 13.2 V IDD Supply Current VDD = 13.2 V 7 mA VI Input Voltages Logical "0" Level Logical "1" Level ± 10 µA Input Bias 4.75 ≤ VDD ≤ 5.25 VDD > 5.25 – 0.3 2.2 VDD – 2 0.8 VDD VDD V V V IB Brightness Input Current (note 2) 0 0.75 mA VB Brightness Input Voltage (pin 9) Input Current = 750 µA Tamb = 25 oC 3 4.3 V VO(off) Off State Output Voltage 13.2 V IO Output Sink Current (note 3) Segment OFF Segment ON VO = 3 V VO = 1 V (note 4) Brightness In. = 0 µA Brightness In. = 100 µA Brightness In. = 750 µA 0 2 12 2.7 15 10 10 4 25 µA µA mA mA fclock Input Clock Frequency 0 0.5 MHz IO Output Matching (note 1) ± 20 % Notes : 1. Output matching is calculated as the percent variation from IMAX + IMIN/2. 2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. 3. Absolute maximum for each output should be limited to 40 mA. 4. The VO voltage should be regulated by the user. FUNCTIONAL DESCRIPTION The M5482 uses the M5451 die which is packaged to operate 2-digit alphanumeric displays with mini- mal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current for LED displays. A 1nF capacitor should be connected to brightness control, Pin 9, to prevent possible oscillations. A block diagram is shown in Figure 1. The output current is typically 20 times greater than the current into Pin 9, which is set by an external variable resistor. There is an internal limiting resistor of 400 Ω nomi- nal value. Figure 2 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches. 36 BIT 34 BIT 35 CLOCK DATA LOAD (INTERNAL) RESET (INTERNAL) START BIT 1 1 Figure 2 : Input Data Format M5482 3/6 |
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