CLOCK

DATA

300ns (min.)

Figure 3

At the low state of the clock a RESET signal is

generated which clears all the shift registers for the

next set of data. The shift registers are static master

slave configurations. There is no clear for the mas-

ter portion of the first shift register, thus allowing

continuous operation.

There must be a complete set of 36 clocks or the

shift registers will not clear.

When power is first applied to the chip an internal

power ON reset signal is generated which resets

all registers and all latches. The START bit and the

first clock return the chip to its normal operation.

Figure 3 shows the timing relationships between

Data and Clock.

A maximum clock frequency of 0.5 MHz is as-

sumed.

Figure 4 shows the Output Data Format for the

M5482. Because it uses only 15 of the possible 35

outputs, 20 of the bits are "Don’t Cares".

For applications where a lesser number of outputs

are used it is possible to either increase the current

Figure 4 : Serial Data Bus / Outputs Correspondance

5451

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

START

5482

15

XXXX

14

13

XXX

X

12

11

10

9

XX

X

START

5451

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

START

5482

X

8765

X

X

X

X

4

3

2

1

X

X

X

X

START

per output or operate the part at higher than 1V

The following equation can be used for calcula-

tions.

(80

where :

°C max)

80

°C/W = thermal coefficient of the package

15 SEGMENTS

M5482

DISPLAY DRIVER

PROCESSOR

KEYBOARD

PLL

SYNTHESIZER

LED DISPLAY

TYPICAL APPLICATION

BASIC electronically tuned TV system.

M5482

4/6