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TPS73233DBVT 数据表(PDF) 41 Page - Texas Instruments |
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TPS73233DBVT 数据表(HTML) 41 Page - Texas Instruments |
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41 / 47 page ![]() www.ti.com EXAMPLE BOARD LAYOUT 5X (2.05) 5X (0.65) 0.2 TYP 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND (6) (2.05) (3.2) 4X (1.27) (R0.05) TYP (1.35) (0.775) TYP SOT - 1.8 mm max height DCQ0006A PLASTIC SMALL OUTLINE 4214845/C 11/2021 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM PKG 1 5 6 METAL SOLDER MASK OPENING EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL |
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