AM261...ZFG datasheet(148/218 Pages) TI2

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SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (IN)

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

PHA=1

EPOL=1

POL=0

POL=1

POL=0

POL=1

SM8

SM9

SM3

SM1

SM2

SM1

SM8

SM9

SM3

SM1

SM2

SM1

SM2

SM3

SM2

SM3

SM4

SM5

SM4

SM5

SM4

SM5

SPRSP08_TIMING_McSPI_02

Figure 6-41. SPI Controller Mode Receive Timing

6.11.5.11.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Normal Mode

SM1

tc(SPICLK)

Cycle time, SPI_SCLK

SM2

tw(SPICLKL)

Typical Pulse duration,

SPI_SCLK low

–1 + 0.5P(1)

SM3

tw(SPICLKH)

Typical Pulse duration,

SPI_SCLK high

–1 + 0.5P(1)

SM6

td(SPICLK-SIMO)

Delay time, SPI_SCLK active

edge to SPI_D[x] transition

–3

SM7

tsk(CS-SIMO)

Delay time, SPI_CS[i] active to

SPI_D[x] transition

SM8

td(SPICLK-CS)

Delay time, SPI_CS[i] active to

SPI_SCLK first edge

PHA = 0

–4 + B(3)

PHA = 1

–4 + A(2)

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

www.ti.com

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