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AM261...ZFG 数据表(PDF) 1 Page - Texas Instruments |
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AM261...ZFG 数据表(HTML) 1 Page - Texas Instruments |
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1 / 218 page ![]() AM261x Sitara™ Microcontrollers 1 Features Processor Cores: • Single and Dual Arm® Cortex® R5F CPU with each core running up to 500MHz – 16KB I-Cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 256KB Tightly Coupled Memory (TCM) with 32- bit ECC per core – Lockstep or Dual-core operation supported • Trigonometric Math Unit (TMU) for accelerating trigonometric functions – Up to 2x, one per R5F MCU core Memory: • 1.5MB of On-Chip Shared RAM (OCSRAM): – 3 banks × 512KB – ECC error protection for full 1.5MB OCSRAM – Remote L2 Cache (RL2) for external memory, software programmable up to 256KB per CPU core • 2x Octal Serial Peripheral Interface (OSPI) up to 133MHz SDR and DDR – 1x with eXecute In Place (XIP) support – RAM expansion/Flash over the Air (FOTA) • General-Purpose Memory Controller (GPMC) – 16-bit parallel data bus with 22-bit address bus and 4 chip selects – Up to 4MB addressable memory space – Integrated Error Location Module (ELM) support for error checking System on Chip (SoC) Services and Architecture: • 1x EDMA to support data movement functions • Device Boot supported from the following interfaces: – UART (Primary/Backup) – OSPI NOR and NAND Flash (50MHz SDR and 25MHz DDR) (Primary) – USB Peripheral boot • Interprocessor communication modules – SPINLOCK module for synchronizing processes running on multiple cores – MAILBOX functionality implemented through CTRLMMR registers • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers • Timer Modules: – 2x Windowed Watchdog Timer (WWDT) – 4x Real Time Interrupt (RTI) timer USB 2.0 • Port configurable as USB host, USB device, or USB Dual-Role device • USB 2.0 Host mode – High-Speed (HS, 480Mbps) – Full-Speed (FS, 12Mbps) – Low-Speed (LS, 1.5Mbps) • USB 2.0 Device mode – High-Speed (HS, 480Mbps) – Full-Speed (FS, 12Mbps) Industrial Connectivity: • 2x Programmable Real-time Unit – Industrial Communication Subsystem (PRU-ICSS) – Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1) per PRU-ICSS for 4 cores total • Deterministic hardware • Dynamic firmware – 20-channel enhanced input (eGPI) per PRU – 20-channel enhanced output (eGPO) per PRU – Embedded Peripherals and Memory • 1x UART, 1x ECAP, 1x MDIO, 1x IEP • 1x 32KB Shared General Purpose RAM • 2x 8KB Shared Data RAM • 1x 12KB IRAM per PRU • ScratchPad (SPAD), MAC/CRC – Digital encoder and sigma-delta control loops – The PRU-ICSS enables advanced industrial protocols including: • EtherCAT®, Ethernet/IP™ • PROFINET®, IO-Link® – Dedicated Interrupt Controller (INTC) – Dynamic CONTROLSS XBAR Integration High Speed Interfaces • Integrated 3-port Gigabit Ethernet Switch (CPSW) supporting up to two external ports – Selectable MII (10/100), RMII (10/100), or RGMII (10/100/1000) – IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP – Clause 45 MDIO PHY management – 512x ALE engine based packet classifiers – Priority flow control with up to 2KB packet size – Four CPU hardware interrupt pacing – IP/ UDP/ TCP checksum offload in hardware – Time Sensitive Network (TSN) Support – Cut-thru switching and Interexpress Traffic (IET) support AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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