AM261...ZFG datasheet(164/218 Pages) TI2

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tO4t

tO3t

tO5t

tO2t

tO1t

OSPI_CSn

OSPI_CLK

OSPI_D[i:0]

Figure 6-60. OSPI Switching Characteristics – PHY DDR

6.11.5.13.3 OSPI Tap Mode

6.11.5.13.3.1 OSPI Tap SDR Timing

6.11.5.13.3.1.1 OSPI Timing Requirements - Tap SDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O19

tsu(D-CLK)

Setup time, OSPI_D[7:0] valid

before active OSPI_CLK edge

No Loopback

10.4 - (0.975 ×

T(1) × R(2))

O20

th(CLK-D)

Hold time, OSPI_D[7:0] valid after

active OSPI_CLK edge

No Loopback

0.7 + (0.975 ×

T(1) × R(2))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = REFCLK cycle time in ns

tO20t

O19

OSPI_CLK

OSPI_D[i:0]

Figure 6-61. OSPI Timing Requirements – Tap SDR, No Loopback

6.11.5.13.3.1.2 OSPI Switching Characteristics - Tap SDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI_CLK

tw(CLKL)

Pulse duration, OSPI_CLK low

0.475P(1) - 0.3

tw(CLKH)

Pulse duration, OSPI_CLK high

0.475P(1) - 0.3

O10

td(CSn-CLK)

Delay time, OSPI_CSn[1:0] active edge

to OSPI_CLK rising edge

0.475P(1) + (0.975

× M(2) × R(4)) - 1

0.525P(1) + (1.025

× M(2) × R(4)) + 1

O11

td(CLK-CSn)

Delay time, OSPI_CLK rising edge to

OSPI_CSn[1:0] inactive edge

0.475P(1) + (0.975

× N(3) × R(4)) - 1

0.525P(1) + (1.025

× N(3) × R(4)) + 1

O12

td(CLK-D)

Delay time, OSPI_CLK active edge to

OSPI_D[7:0] transition

–4.25

7.25

(1)

P = CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = REFCLK cycle time in ns

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

www.ti.com

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AM261...ZFG 数据表(PDF) 164 Page - Texas Instruments

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