AM261...ZFG datasheet(104/218 Pages) TI2

104 / 218 page

VDDSHV_x (3.3V)

POWER GOOD (1.2V/1.25V, 1.8V, 3.3V)

PORZ

SOP[3:0]

tSAMPLED_SOP

tSU_SOP

tH_SOP

WARMRSTZ

VDDSHV_x (1.8V)

tRAMP_3V3

VDD, VDDARx, VNWA(1.2V/1.25V)

tRAMP_1V8

tDELAY_3V3

tDELAY_PG

tRAMP_1V2

tWARMRSTZ

Figure 6-2. Power-On Sequencing

6.11.2.1.1 Power Reset Sequence Description

The following set of steps shall occur on the EVM and AM261x to boot the device from power-on reset.

1. PORz is held low by the external power supply monitor

2. VDDSHV_x 3.3V supply ramps to its nominal voltage

a. This requires a logical AND be applied to the power good signal generated from each supply

3. Delay at least 50μs after VDDSHV_x 3.3VB is at valid range

4. VDDSHV_x 1.8V and VDD 1.2V/1.25V supplies ramp to their nominal voltages (no constraint on order of

1.8V and 1.2V/1.25V ramp)

5. SOP[3:0] pins held in their boot latch state

6. Power-Good supervisor output triggers based on valid 3.3V, 1.8V, and 1.2V/1.25V all being at valid range

7. PORz low to high transition is triggered by Power-Good supervisor output

a. Warm Reset output will toggle low to high tWARMRSTZ seconds after PORz transition

8. After internal supply monitors show externally and internally generated supplies are stable, the SOP[3:0] pin

states are latched

9. R5F cores are unhalted and SOP selected boot ROM execution begins

AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

www.ti.com

104

Submit Document Feedback

Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1

AM261...ZFG 数据表(PDF) 104 Page - Texas Instruments

AM261...ZFG 数据表(HTML) 104 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载