STPM11ATR datasheet(32/45 Pages) STMICROELECTRONICS

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Theory of operation

STPM11/12/13/14

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t1 →t2 (>30ns): CFGI out of idle state

t2 →t3 (>30ns): CFGI enabled for write operation

t3: data value is placed in SDA

t4: SDA value is stable and shifted into the device

t3 →t5 (>10µs): writing Clock period

t3 →t5: 1 bit Data value

t5 →t6: 6 bits address of the destination latch

t6 →t7: 1 bit EXE command

t8: end of CFGI writing

t9: CFGI enters idle state

The same procedure should be applied for the mode signals, but in this case the 6-bits

address must be taken from the Table 14.

The lsb of command is also called EXE bit because instead of data bit value, the

corresponding serial clock pulse is used to generate the necessary latching signal. In this

way the writing mechanism does not need the measurement clock in order to operate, which

makes the operation of CFGI module of STPM1x completely independent from the rest of

the device logic except from the signal POR.

Commands for changing system signals should be sent during active signals SCS and SYN-

NP as it is shown in the Figure 19 -. A string of commands can be send within one period of

active signals SCS and SYN-NP.

Permanent writing of the CFG bits

In order to make a permanent set of some CFG bits, use the following procedure:

1. collect all addresses of CFG bits to be permanently set into a list;

2. clear all OTP shadow latches;

3. set the system signal RD;

4. connect a current source of at least +14V, 1mA to 3mA to VOTP;

5. wait for VOTP voltage to be stable;

6. set one OTP shadow latch from the list;

7. set the system signal WE;

8. wait for 300 s;

9. clear the system signal WE;

10. clear the OTP shadow latch which was set in step 6;

11. until all CFG bits are permanently set as desired, repeat steps 5 to 11;

12. disconnect the current source;

13. wait for VOTP voltage to be less than 3V;

14. clear the system signal RD;

15. verify the correct writing, testing STPM1x operation;

16. if the verification of CFG bits fails, repeat steps 1 to 16.

For steps of set or clear, apply the timing shown in Figure 19 - with proper signal on the

SDA-TD.

In order to create a permanent set of the TSTD bit, which does not result in any more writing

to the Configuration bits, the procedure above must be conducted in such a way that steps 6

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