C8051F310 datasheet(71/228 Pages) SILABS

71 / 228 page

Rev. 1.7

C8051F310/1/2/3/4/5/6/7

Figure 7.3. Comparator Hysteresis Plot

The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for

n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and

the positive and negative-going symmetry of this hysteresis around the threshold voltage.

The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN

(shown in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is

determined by the settings of the CPnHYN bits. As shown in Table 7.1, settings of 20, 10 or 5 mV of

negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the

amount of positive hysteresis is determined by the setting the CPnHYP bits.

Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-

rupt enable and priority control, see Section “8.3. Interrupt Handler” on page 93). The CPnFIF flag is set

to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to logic 1 upon the Compar-

ator rising-edge interrupt. Once set, these bits remain set until cleared by software. The output state of the

Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by set-

ting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.

The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-

ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.

Note that false rising edges and falling edges can be detected when the comparator is first powered-on or

if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the

rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is

enabled or its mode bits have been changed. This Power Up Time is specified in Table 7.1 on page 78.

Positive Hysteresis Voltage

(Programmed with CP0HYP Bits)

Negative Hysteresis Voltage

(Programmed by CP0HYN Bits)

VIN-

VIN+

INPUTS

CIRCUIT CONFIGURATION

CP0+

CP0-

CP0

VIN+

VIN-

OUT

VOH

Positive Hysteresis

Disabled

Maximum

Positive Hysteresis

Negative Hysteresis

Disabled

Maximum

Negative Hysteresis

OUTPUT

VOL

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