C8051F310 datasheet(34/228 Pages) SILABS

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C8051F310/1/2/3/4/5/6/7

Rev. 1.7

1.8.

Comparators

C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via

user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator

outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.

Comparator response time is programmable, allowing the user to select between high-speed and low-

power modes. Positive and negative hysteresis are also configurable.

Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-

rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.

Figure 1.16 shows he Comparator0 block diagram.

Figure 1.16. Comparator0 Block Diagram

VDD

Reset

Decision

Tree

Crossbar

Interrupt

Logic

SET

CLR

SET

CLR

(SYNCHRONIZER)

GND

CP0 +

P1.0

P1.4

P2.0

P2.4

CP0 -

P1.1

P1.5

P2.1

P2.5

CP0EN

CP0OUT

CP0RIF

CP0FIF

CP0HYP1

CP0HYP0

CP0HYN1

CP0HYN0

CMX0N1

CMX0N0

CMX0P1

CMX0P0

CP0RIE

CP0FIE

CP0MD1

CP0MD0

CP0

CP0A

CP0

Rising-edge

CP0

Falling-edge

CP0

Interrupt

C8051F310 数据表(PDF) 34 Page - Silicon Laboratories

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