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MPC8313E 数据表(PDF) 21 Page - Freescale Semiconductor, Inc

部件名 MPC8313E
功能描述  PowerQUICC??II Pro Processor Hardware Specifications
PDF  92 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8313E 数据表(HTML) 21 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
21
DUART
7DUART
This section describes the DC and AC electrical specifications for the DUART interface.
7.1
DUART DC Electrical Characteristics
Table 21 provides the DC electrical characteristics for the DUART interface.
7.2
DUART AC Electrical Specifications
Table 22 provides the AC timing parameters for the DUART interface.
8
Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII
management.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all the media independent interface (MII), reduced
gigabit media independent interface (RGMII), serial gigabit media independent interface (SGMII), and
reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management
data clock (MDC). The MII interface is defined for 3.3 V, while the RMII, RGMII, SGMII, and RTBI
Table 21. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2.0
NVDD + 0.3
V
Low-level input voltage NVDD
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μAVOH
NVDD – 0.2
—
V
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
Input current (0 V
≤VIN ≤ NVDD)IIN
—± 5
μA
Table 22. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
256
baud
—
Maximum baud rate
> 1,000,000
baud
1
Oversample rate
16
—
2
Notes:
1. Actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit.
Subsequent bit values are sampled each 16th sample.



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