MPC8313E datasheet(83/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

System Design Information

measured voltage is V2 =(1/(1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource =

Rterm × (V1/V2 – 1). The drive current is then Isource =V1/Rsource.

Table 69 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,

nominal NVDD, 105°C.

21.7

Configuration Pin Muxing

The MPC8313E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is

disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections

to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should

minimize the disruption of signal quality or speed for output pins thus configured.

21.8

Pull-Up Resistor Requirements

The MPC8313E requires high resistance pull-up resistors (10 k

Ω is recommended) on open drain type pins

including I2C pins, Ethernet Management MDIO pin and EPIC interrupt pins.

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 46. Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions because most have asynchronous behavior and spurious assertion,

which give unpredictable results.

Refer to the PCI 2.2 specification for all pull-ups required for PCI.

21.9

JTAG Configuration Signals

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in

IEEE 1149.1, but is provided on all processors that implement the PowerPC architecture. The device

requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere

with normal chip operation. While it is possible to force the TAP controller to the reset state using only the

TCK and TMS signals, systems generally assert TRST during power-on reset. Because the JTAG interface

Table 69. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(not including PCI

output clocks)

PCI Output Clocks

(including

PCI_SYNC_OUT)

DDR DRAM

Symbol

Unit

42 Target

25 Target

42 Target

20 Target

42 Target

25 Target

42 Target

20 Target

Differential

ZDIFF

Note: Nominal supply voltages. See Table 1, Tj = 105°C.

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