AI01869C

E

G

W

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWH

tGHWL

RB

tWHRL

Figure 7. Write AC Waveforms, W Controlled

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

POWER SUPPLY

Power Up

The memory Command Interface is reset on power

during Power Up to allow maximum security and

the possibility to write a command on the first rising

edge of E and W. Any write cycle initiation is

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

µF capacitor

gram and erase currents required.

20/34

M29F400T, M29F400B