APM32F103TBU7-R datasheet(50/78 Pages) GEEHY

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P a g e 49

Figure 17 SPI Timing Diagram - Master Mode

High

NSS input

MOSI

output

MISO input

MSB IN

MSB OUT

BIT 6~1 IN

LSB IN

LSB OUT

BIT 6~1 OUT

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

tc(SCK)

th(MI)

tv(MO)

th(MO)

SCK input

tW(SCKH)

tW(SCKL)

tSU(MI)

tr(SCK)

tf(SCK)

Note: The measuring points are set at CMOS levels: 0.3VDD and 0.7VDD.

5.11.3 USBD peripheral characteristics

Table39 USBD DC Characteristics

Symbol

Parameter

Condition

Minimum

value (1)

Maximum

value (1)

Unit

Input level

VDD

USBD operating

voltage (2)

3.0

（3）

3.6

VDI

（4）

Differential input

sensitivity

I (USBDP, USBDM)

0.2

VCM

（4）

Differential common

mode range

Including VDI range

0.8

2.5

VSE

（4）

Single-ended receiver

threshold

1.3

2.0

Output level

VOL

Static output low level

1.5kΩ RL connected to 3.6V

(5)

0.3

VOH

Static output high

level

5kΩ RL connected to VSS (5)

2.8

3.6

All voltage measurement is subject to device-end ground wire.

In order to be compatible with the USB2.0 full-speed electrical specification, the USBDP (D+) pin must

be connected to a voltage of 3.0~3.6V through a 1.5kΩ resistor.

The correct USBD function of APM32F103xx can be guaranteed at 2.7V, rather than the electrical

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