APM32F103RBT7-R datasheet(20/78 Pages) GEEHY

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P a g e 19

4.3.2

External Interrupt/Event Controller (EINT)

The external interrupt/event controller consists of 19 edge detectors that generate

event/interrupt requests. Its trigger events (rising edge or falling edge or double edge) can be

independently configured or shielded; there is a suspend register that maintains the status of

all interrupt requests. Up to 80 general-purpose I/O can be connected to 16 external interrupt

lines. EINT can detect that the pulse width is less than the clock cycle of the internal APB2.

4.4

Memory

The memory includes main memory area, SRAM and information block; the information block

includes system memory area and option byte; the system memory area stores BootLoader,

96-bit unique device ID and capacity information of main memory area; the system memory area

has been written into the program when leaving the factory and cannot be erased.

Table5

Memory

Maximum

bytes

Function

Main memory area

128 KB

Store user programs and data

SRAM

36KB

Can be accessed by byte, half word (16 bits) or word (32 bits).

System memory

area

2 KB

Store BootLoader, 96-bit unique device ID, and main memory area

capacity information

Option byte

16Bytes

Configure main memory area read-write protection and MCU

working mode

4.5

Clock

4.5.1

Clock tree

The clock tree of APM32F103xB series is shown in the figure below:

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