OUTPUT GAIN SET: DESIGN CONSIDERA-

TIONS (refer to figure 4)

PWRO+ and PWRO– are low impedance comple-

mentary outputs. The voltages at the nodes are:

R1 and R2 are a gain setting resistor network with

value greater than 10K

Ω and less than 100KΩ for

R1 + R2 is recommended because:

a) The parallel combination of R1 + R2 and RL

sets the total loading.

parallel combination of R1 and R2 define a

time constant which has to be minimized to

avoid inaccuracies.

If VA represents the output voltage without any

gain setting network connected, you can have:

where A =

1

4

For design purposes, a useful form is R1/R2 as a

function of A.

R1 / R2 =

4A –

1

(allowable values for A are those which make

R1/R2 positive)

Examples are:

If A = 1 (maximum output), then

R1/R2 =

If A = 1/2. then

R1/R2 = 2

If A = 1/4 (minimum output) then

i.e., GSR is tied to PWRO+

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

DIGITAL INTERFACE

Low Level Input Current

GRDD

10

µA

High Level Input Current

10

µA

Input Low Voltage, Except CLKSEL

0.8

V

Input High Voltage, Except CLKSEL

2.0

V

Output Low Voltage

0.4

V

Output High Voltage

2.4

V

Input Low Voltage, CLKSEL (note 2)

0.5

V

Input Intermediate Voltage, CLKSEL

GRDD

-0.5

0.5

V

Input High Voltage, CLKSEL

0.5

VCC

V

Digital Output Capacitance (note 3)

5

pF

Digital Input Capacitance

5

10

pF

Notes:

3. Timing parameters are guaranteed based on a 100pF load capacitance.

Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60pF.

M5913

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