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PRELIMINARY DATA

October 1999

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M59DR032A

M59DR032B

32 Mbit (2Mb x16, Dual Bank, Page) Low Voltage Flash Memory

s

SUPPLY VOLTAGE

Erase and Read

Program and Erase

s

ASYNCHRONOUS PAGE MODE READ

– Page Width: 4 words

– Page Access: 35ns

– Random Access: 100ns

s

PROGRAMMING TIME

– 10µs by Word typical

– Double Word Programming Option

s

MEMORY BLOCKS

– Dual Bank Memory Array: 4 Mbit - 28 Mbit

– Parameter Blocks (Top or Bottom location)

– Main Blocks

s

DUAL BANK OPERATIONS

– Read within one Bank while Program or

Erase within the other

– No delay between Read and Write operations

s

BLOCK PROTECTION/UNPROTECTION

– All Blocks protected at Power Up

– Any combination of Blocks can be protected

–WP for Block Locking

s

COMMON FLASH INTERFACE (CFI)

s

64 bit SECURITY CODE

s

ERASE SUSPEND and RESUME MODES

s

100,000 PROGRAM/ERASE CYCLES per

BLOCK

s

20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

s

ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code, M59DR032A: A0h

– Device Code, M59DR032B: A1h

BGA

TSOP48 (N)

12 x 20mm

FBGA48 (ZB)

8 x 6 solder balls

Figure 1. Logic Diagram

AI02544B

21

A0-A20

W

DQ0-DQ15

VDD

M59DR032A

M59DR032B

E

VSS

16

G

RP

WP

VDDQ VPP