M59DR016 datasheet(2/37 Pages) STMICROELECTRONICS

2 / 37 page

M59DR016C, M59DR016D

2/37

Figure 2. TFBGA Connections (Top view through package)

AI04113

VPP

A11

A13

DQ8

DQ5

DQ14

A16

VSS

DQ0

DQ9

DQ3

DQ6

DQ15

VDDQ

DQ1

DQ10

VDD

DQ7

VSS

DQ2

A17

A10

A14

A12

A15

A18

DQ4

DQ13

DQ12

DQ11

A19

Table 1. Signal Names

A0-A19

Address Inputs

DQ0-DQ15

Data Input/Outputs, Command Inputs

Chip Enable

Output Enable

Write Enable

Reset/Power Down

Write Protect

VDD

Supply Voltage

VDDQ

Supply Voltage for Input/Output

Buffers

VPP

Optional Supply Voltage for

Fast Program & Erase

VSS

Ground

Not Connected Internally

DESCRIPTION

The M59DR016 is a 16 Mbit non-volatile Flash

memory that may be erased electrically at block

level and programmed in-system on a Word-by-

Word basis using a 1.65V to 2.2V VDD supply for

the circuitry. For Program and Erase operations

the necessary high voltages are generated inter-

nally. The device supports asynchronous page

mode from all the blocks of the memory array.

The array matrix organization allows each block to

be erased and reprogrammed without affecting

other blocks. All blocks are protected against pro-

gramming and erase at Power Up. Blocks can be

unprotected to make changes in the application

and then reprotected.

Instructions for Read/Reset, Auto Select, Write

Configuration

Programming,

Block

Erase, Bank Erase, Erase Suspend, Erase Re-

sume, Block Protect, Block Unprotect, Block Lock-

ing, CFI Query, are written to the memory through

a Command Interface using standard micropro-

cessor write timings.

The device is offered in TFBGA48 (0.75 mm pitch)

packages and it is supplied with all the bits erased

(set to ‘1’).

M59DR016 数据表(PDF) 2 Page - STMicroelectronics

M59DR016 数据表(HTML) 2 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载