TDA7541 datasheet(39/76 Pages) STMICROELECTRONICS

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TDA7541

Functional description

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Low noise CMOS op-amp

An internal voltage divider at pin19 connects the positive input of the low noise op-amp. The

charge pump output connects the negative input. This internal amplifier in cooperation with

external components can provide an active filter. The negative input is switchable to two

input pins, to increase the flexibility in application. While the high current mode is activated

LPHC output is switched on.

Antenna DAC

For tuning of FM antenna tank circuit two different modes are available (TVM). One is the

auto-alignment measurement of VCO tuning voltage with offset of 8-bit DAC (TVO). The

other one is an adjustment of 8-bit DAC independent on PLL tracking. For big differences

between VCO tuning voltage and antenna tank control voltage an additional constant offset

voltage can be switched to antenna circuit (TVO+).

4.4.2

IF counter block

The aim of IF counter is it to measure the intermediate frequency of the tuner. The input

signals are the output level of 10.7MHz IF-limiter in FM and output level of 450KHz IF-limiter

in AM.

The grade of integration is adjustable by different measuring cycle times (IFS). The

tolerance of the accepted count value is adjustable too (EW), to reach an optimum

compromise for search speed and precision of the evaluation.

Sampling timer

A sampling timer generates the gate signal for the main counter. The basically sampling

time are in FM 6.25 kHz (tTIM=160 s) and in AM 1 kHz (tTIM=1ms). This is followed by an

asynchronous divider to generate several sampling times.

Intermediate frequency main counter

This counter is an 11 - 21-bit synchronous auto reload down counter. The counter length is

automatic adjusted to the chosen sampling time and the counter mode (FM or AM).

At the start the counter will be loaded with a defined value which is an equivalent to the

divider value (tSample x fIF).

If a correct frequency is applied to the IF counter frequency input at the end of the sampling

time the main counter is changing its state. This is detected by control logic and an external

search stop output is changing from LOW to HIGH.

The IF counter is started only by the in lock information from the PLL part.

4.5

I2C bus interface

The TDA7541 supports the I2C bus protocol. This protocol defines any device that sends

data onto the bus as a transmitter, and the receiving device as the receiver. The device that

controls the transfer is a master and device being controlled is the slave. The master will

always initiate data transfer and provide the clock to transmit or receive operations.

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