RA4E1 datasheet(6/81 Pages) RENESAS

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1.2

Block Diagram

Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the

features.

Memory

512 KB code flash

8 KB data flash

128 KB SRAM

DMA

DMAC × 8

System

Mode control

Power control

protection

MOSC/SOSC

Clocks

(H/M/L) OCO

PLL/PLL2

Battery backup

GPT32 x 2

GPT16 x 2

Timers

AGT × 5

RTC

Arm Cortex-M33

DTC

CAC

POR/LVD

Reset

ELC

Event link

SCE9*1

Security

Analog

CRC

Data processing

DOC

Communication interfaces

QSPI

IIC

SPI

CAN

USBFS

SCI × 4

DAC12

ADC12

1 KB Standby

SRAM

Bus

MPU

ICU

WDT/IWDT

MPU

NVIC

System timer

Test and DBG interface

IDAU

DSP

FPU

Note:

Not available on all parts.

Note 1. Only access control circuit, random number generation circuit, and unique ID are supported. The operation of other

circuits is not guaranteed.

Figure 1.1

Block diagram

1.3

Part Numbering

Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a

list of products.

RA4E1 Datasheet

1. Overview

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

Page 6 of 81

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